The computational power achieved in modern general-purpose computers is primarily attributed to the high switching speed and small signal delays of the semiconductor microcircuits, whereas the structure of their basic architectures has remained relatively unchanged. The conventional von Neumann computer architecture suffers from a serious fundamental handicap which is due to its method of addressing memory. Memory is accessed serially by location, and that addressing approach consumes a great deal of time and leaves a vast proportion of the memory hardware idle. Also, much time is spent on purely searching and sorting tasks needed for memory management. One alternative is to use Content-Addressable Memories (CAMs) in a computational data base.
A content-addressable memory is defined to be a storage device that stores data in a number of cells which can be accessed or loaded on the basis of their contents. In its simplest form, a CAM can be used to store and access data according to address location and also to determine the address location of presented data. These are the Write, Read, and Search operations, respectively. The memory can be made more powerful by incorporating additional logic whereby a "don't care" state, as well as the "1" and "0" states, can be presented to the CAM so that certain bits can be masked from the search operation. Additional flexibility results from the ability to store the "don't care" state in the memory itself.
For speed and simplicity, all cells are compared simultaneously in parallel, and a single mismatch on any of the cells signals a mismatch for the entire word. With the parallel approach, the data must be stored such that a search operation will not destroy it. To do this, the data should be stored on an active device in such a way that when a "mismatch" is presented, the device changes its output while retaining its state.
The storage can be achieved in a number of ways. Presently, however, insulated gate field effect transistor (IGFET) technologies are most attractive when density, speed, power dissipation and cost are taken into account. It is convenient to build the memory cell and the support circuitry in the same technology. Therefore, the active device of greatest interest is the IGFET. At a minimum, the cell needs to be able to signal exact matches or mismatches, as well as have the capability to be externally masked. Therefore, three possible states must be presented to it, requiring two bitlines in a binary system. Since the IGFET is a unidirectional device and there are two bitlines which need to be compared, at least two active devices are needed. In summary, the minimum requirements for an IGFET CAM cell are: (1) two FETs to store data, (2) two bitlines for `1`, `0`, and "don't care" comparisons, (3) an output line to signal a match or mismatch, and (4) a means to store charge on the gates of the two FETs.
In the usual CAM cell design there are two bitlines that run vertically through all the words in the column; those bitlines are used both to carry data to be written into the cells and to present data against which a match is to be made. A Match line runs horizontally connecting an entire word and serves as a wired-or for mismatches. The Match line remains high if each cell in the CAM word matches the presented data on the bitlines. Conversely, if any cell in the word mismatches the presented data, the Match line is discharged to a lower potential. The Match line is also used to read the CAM word during the refresh operation. A Write line passes through each cell to provide a means for isolating all but the cells of interest from a write cycle.
One CAM cell design is presented by Joseph L. Mundy in U.S. Pat. No. 3,701,980 and is shown here in FIG. 2. To write to this cell, the data is stored on the M.sub.S transistors and is accessed using the M.sub.W transistors. Writing is accomplished by choosing a particular word, raising its Write line to a high potential, and driving the desired logic levels on the bit 1 and bit 0 lines. The M.sub.W transistors are turned on by the Write signal to allow the gates of the M.sub.S transistors to be charged or discharged through the bit lines. A logic level "1" for the cell might be recognized as a high potential on M.sub.S1 and a low potential on M.sub.S0. A logic "0" would be the inverse low potential on M.sub.S1 and high potential on M.sub.S0. An internal "don't care" mask can be made by discharging both M.sub.S transistor gates.
Searching is accomplished by holding the Match line at a high potential while the bitlines are moved to their desired potentials. If a bitline is lowered on a branch where a high potential is stored on the gate of the M.sub.S transistor, current flows from the Match line through the "on" MS transistor to the bitline and a mismatch is detected. For example, if M.sub.S1 has a high potential stored on its gate and is thus "on" and the bit 1 line is lowered, current flows from the Match line. If no current flows from any of the bits in a word, a match is detected.
Addressed Reading is required to refresh the cell and is accomplished by keeping the Write line and the two bit lines at ground and raising the potential of the Match line for a specific word. Current then flows on a bit line if it is on a branch with a high potential stored on the M.sub.S transistor. It is interesting to note that the search and read cycles are essentially the same except that the roles of the Match and bit lines are interchanged. Refresh is accomplished using a word-by-word Read and Write refresh cycle.
The Mundy cell has the advantages and disadvantages that one would expect of a dynamic memory design. The cell is quite dense and has fast current driven Read and Search operations. Due to its dynamic nature, however, it requires a word-by-word Read-Write refresh cycle.